This invention relates to a semiconductor integrated circuit device suitable for the output circuit of a semiconductor memory having a plurality of output bits.
In a device, such as a semiconductor memory having a plurality of output bits, and thus having a plurality of output circuits including transistors which are large in current drive capacity for external circuits, when these output circuits operate simultaneously, significant noise is induced by inductance of a power source line, a grounding line and the like thus causing erroneous operations such as errors in writing data and oscillations. This difficulty has been eliminated by the provision of an intermediate potential setting circuit in which the output terminal is held at an intermediate potential prior to outputting data, so that the charging or discharging current accompanying variation of the output is decreased in peak value.
FIG. 3 shows an example of such conventional intermediate potential setting circuit. In FIG. 3, reference numeral 1 designates an output MOSFET circuit comprising a P-type MOSFET Q3 and an N-type MOSFET Q4, and 2, an intermediate potential setting circuit comprising N-type MOSFETs Q2 and Q13. Further in FIG. 3, reference character DP designates a first output control signal; DN, a second output control signal; PS1, a third output control signal; Dout, an output terminal; CL, a load capacitor; Vcc, a power source line; and GND, a ground line.
In operation, in order to give an intermediate potential to the output terminal Dout, first the first output control signal DP is raised to a high level (hereinafter referred to merely as "H", when applicable) while the second output control signal DN is set to a low level (hereinafter referred to merely as "L", when applicable). In this operation, both of the MOSFETs Q3 and Q4 forming the output MOSFET circuit 1 are non-conductive (off), and the output terminal Dout is held at "H" or "L" depending on whether or not the load capacitor CL is charged. Then, the third output control signal PS1 is raised to "H". In this connection,
(1) if the output terminal Dout is initially at "L", the drain, gate and source of the N-type MOSFET Q2 are "H", "H" and "L", respectively, and therefore the MOSFET Q2 is conductive (on). Accordingly, a charging current flows from the line to which the first output control signal DP is applied, through the MOSFET Q2 into the load capacitor CL, so that the potential of the output terminal Dout is raised.
(2) On the other hand, the drain, gate and source of the N-type MOSFET Q13 are initially held at "L", "H" and "L", respectively, and therefore the MOSFET Q13 is non-conductive (off). However, the potential of the output terminal Dout of the drain increases as described above (paragraph (1)) and when it exceeds the threshold voltage Vth of the MOSFET Q13, the MOSFET Q13 is rendered conductive (on). Therefore, a through current in addition to the charging current flows in the MOSFETs Q2 and Q13. In this operation, as the source of the MOSFET Q13 is maintained at "L", the threshold voltage Vth is free from a substrate bias effect, and the channel resistance of the MOSFET Q13 is decreased as the potential of the output terminal Dout of the drain increases. The term "substrate bias effect" as used herein is intended to mean that, when the substrate is reverse-biased, i.e., when the potentials of the source and the drain of an N-type MOSFET are made higher than the ground potential, or when the potentials of the source and the drain of a P-type MOSFET are made lower than the power source potential, the threshold value is increased and the channel resistance is increased. On the other hand, the channel resistance of the MOSFET Q2 is minimum immediately after it is made conductive (on) and increases as the potential of the output terminal Dout of the source increases. As is apparent from the above description, it is impossible to make the sum of the channel resistances of the MOSFETs Q2 and Q13 large from when the intermediate potential setting signal PS1 is applied, and therefore a relatively large through current flows from the beginning of the intermediate potential setting period.
(3) Finally, the channel resistance of the MOSFETs Q2 and Q13 are made constant, so that the output terminal Dout is held at an intermediate potential which is determined by these channel resistances.
(4) In the case where the output terminal Dout is initially held at "H", first the MOSFET Q13 is turned on, so that a discharging current flows from the load capacitor CL through the MOSFET Q13 to the line to which the second output control signal DN is applied, and accordingly the potential of the output terminal Dout is decreased.
(5) On the other hand, the N-type MOSFET Q2 is non-conductive (off) because the source and the drain thereof are at "H"; however, it is rendered conductive (on) when the drain-source voltage becomes higher than the threshold voltage Vth as a result of the decrease of the potential of the output terminal Dout. However, since the threshold voltage Vth is affected by the aforementioned substrate bias effect, the channel resistance of the N-type MOSFET Q2 is higher than that of the MOSFET Q13 even after the MOSFET Q2 is turned on. Accordingly, the through current provided when the potential of the output terminal Dout is changed from "H" to the intermediate potential is smaller than that provided when the potential of the output terminal Dout is changed from "L".
As was described above, after the potential of the output terminal is set to the intermediate potential from "H" or "L", the third output control signal PS1 is set to "L", and the potentials of the first and second output control signals DP and DN are newly set, so that the data is provided at the output terminal Dout.
However, the above-described semiconductor integrated circuit device is disadvantageous in that, since the intermediate potential setting MOSFET circuit is made up of the N-type MOSFETs as was described above, the through currents flowing in these MOSFETs are relatively large, and especially, a large amount of current is consumed when the potential of the output terminal is changed from "L" to the intermediate potential.